1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
A conventional N-channel LDMOS (Lateral Diffused MOS) will be described. The N-channel LDMOS includes a gate electrode formed above a well in a silicon substrate, a P-type body diffusion layer formed in the well to one side of the gate electrode so as to overlap with the gate electrode, a channel region formed in the P-type body diffusion layer and located under the gate electrode, a plurality of P+-type body contact regions and an N+-type source diffusion layer formed in the P-type body diffusion layer, and an N+-type drain diffusion layer formed in the silicon substrate to the other side of the gate electrode (see JP-A-2010-16155, for example).
An interlayer insulation film is formed over the well, the P-type body diffusion layer, and the gate electrode. A first contact hole that establishes contact with the N+-type source diffusion layer, a second contact hole that establishes contact with the N+-type drain diffusion layer, and a third contact hole that establishes contact with the P+-type body contact region are formed in the interlayer insulation film.
In the above N-channel LDMOS, reduction of resistance between the N+-type source diffusion layer and the N+-type drain diffusion layer is required in order to facilitate the flow of a large current. This can be favorably achieved by increasing the number of first contact holes and second contact holes.